:To implement VM without an MMU basically requires emulating every memory reference instruction.
2.
The CPUs in these models introduced vector gather / scatter memory reference instructions to the product line.
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These temps need extra memory reference instructions which take more code space than for the belt machine.
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These temporary locations require extra memory reference instructions which take more code space than for the stack machine, or even compact register machines.
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The machine instructions can be grouped into six categories : accumulator instructions, branch instructions, memory reference instructions, address register instructions, scratchpad register instruction, miscellaneous instructions ( interrupt, input, output, indirect scratchpad register, load, and store ).
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In these architectures, only a very few " memory reference instructions " can access main memory and only for the purpose of loading data into registers or storing register data back into main memory; only a few addressing modes may be available, and these modes may vary depending on whether the instruction refers to data or involves a transfer of control ( jump ).
7.
A Cyber 170-series system consisted of one or two CPUs that ran at either 25 or 40 MHz, and was equipped with 10, 14, 17, or 20 peripheral processors ( PP ), and up to 24 high-performance channels for high-speed I / O . Due to the relatively slow memory reference times of the CPU ( in some models, memory reference instructions were slower than floating-point divides ), the higher-end CPUs ( e . g ., Cyber-74, Cyber-76, Cyber-175, and Cyber-176 ) were equipped with eight or twelve words of high-speed memory used as an instruction cache.
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